library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity impedancia is
Port ( 
liga : in std_LOGIC_vector (3 downto 0);
M : in std_logic_vector (3 downto 0);
I : in std_logic_vector (3 downto 0);
microinst : in std_logic_vector (1 downto 0);
Salida : out std_logic_vector (3 downto 0));
end impedancia;
architecture Behavioral of impedancia is
constant x : std_logic_vector := B"0000";
begin
process(microinst)
begin
--if rising_edge (clk) then
			if(microinst="00")
				then Salida <= x;
			elsif (microinst="01")
				then Salida <= liga;
			elsif (microinst="10")
				then Salida <= M;
			elsif (microinst="11")
				then Salida <= I;
			end if;
--		end if;
end process;
end Behavioral;